The present invention relates to determining I/O pin placement for programmable logic devices or other similar devices.
Programmable logic devices (“PLDs”) (also sometimes referred to as CPLDs, PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, FPGAs, or by other names), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices are well known in the art and typically provide an “off the shelf” device having at least a portion that can be electrically programmed to meet a user's specific needs. Application specific integrated circuits (“ASICs”) have traditionally been fixed integrated circuits, however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.
As PLDs become more complex and flexible, there is an increasing need for the same device to support several different I/O standards. In a typical device, a group of pads sometimes referred to as a “bank” will share a common power source (“VCCIO”) for driving signals off-chip, a common reference voltage (“VREF”) for referencing input signals when applicable (not all banks necessarily support use of a reference voltage) and, when applicable, common termination circuitry. Because of the increasing need to support several standards on a single chip, not all I/O banks on will necessarily support the same standard or set of standards. Some standards are not compatible and must be supported on different banks.
Furthermore, the need for an increased density of I/O connections has led to an increased density of pads (i.e., access points where a pin may be placed) on a chip. This increased density of pads causes current density limits to be approached and these current density limits must be accounted for when placing pins at particular pads. Thus, for particular current requirements of particular pins, there may be a limit on how many consecutive pads in a single bank can accommodate such pins. There is a need for an efficient method to maximize pin density within the constraints imposed by current limits.
The need to accommodate multiple I/O standards and to maximize pin density without violating current density limits has made I/O pin placement increasingly difficult. Past methods have treated I/O pins individually for placement purposes and have not addressed current density limits in a manner that adequately maximizes pin density. An improved method is needed to achieve more efficient and effective pin placement.